##probe failure
#define TLB_INDEX_P_OFFSET 31
#define TLB_INDEX_P_MAKS 0x80000000

#define TLB_INDEX_INDEX_OFFSET 0
#define TLB_INDEX_INDEX_MASK 0x3F


#define TLB_ENTRYLO_R_OFFSET 30
#define TLB_ENTRYLO_R_MASK   0xC0000000

#define TLB_ENTRYLO_PFN_OFFSET 6
#define TLB_ENTRYLO_PFN_MASK   0x3FFFFC0

##cache coherency
##3 WB Cacheable, noncoherent, write-back, write allocate
##4 CWBE Cacheable, write-back, write-allocate, coherent, read misses request Exclusive
##5 CWB Cacheable, write-back, write-allocate, coherent, read misses request Shared 
##6 - Reserved
##7 UCA Uncached Accelerated
##
#define TLB_ENTRYLO_C_OFFSET 3
#define TLB_ENTRYLO_C_MASK   0x38

##dirt or writable
#define TLB_ENTRYLO_D_OFFSET 2
#define TLB_ENTRYLO_D_MASK   0x4
##valid bit
#define TLB_ENTRYLO_V_OFFSET 1
#define TLB_ENTRYLO_V_MASK   0x2

##global
#define TLB_ENTRYLO_G_OFFSET 0
#define TLB_ENTRYLO_G_MASK   0x1

#define TLB_ENTRYHI_VPN2_OFFSET  13
#define TLB_ENTRYHI_VPN2_MASK    0xFFFFE000
#define TLB_ENTRYHI_EHINV_OFFSET 10
#define TLB_ENTRYHI_EHINV_MASK   0x400
#define TLB_ENTRYHI_ASID_OFFSET  0
#define TLB_ENTRYHI_ASI_MASK     0xFF


##entry_lo0.reg.field.d = 1;
##entry_lo0.reg.field.v = 1;
##entry_lo0.reg.field.g = 1;
##entry_lo0.reg.field.c = 5;
##entry_lo1.reg.field.d = 1;
##entry_lo1.reg.field.v = 1;
##entry_lo1.reg.field.g = 1;
##entry_lo1.reg.field.c = 5;
##entry_hi.reg.field.asid = 0x1f;
##pagemask = 0x0;
##
##entry_hi.reg.field.vpn2 = (v_addr + (0x2000 * i)) >> 13;        
##entry_lo0.reg.field.pfn = (phy_addr +(0x2000 * i)) >> 12;
##entry_lo1.reg.field.pfn = (phy_addr +(0x2000 * i)+0x1000) >> 12;

##tlb->tlb[i].pagemask = pagemask;
##tlb->tlb[i].entryhi = entry_hi.reg.all;
##tlb->tlb[i].entrylo0 = entry_lo0.reg.all;
##if ((i == (pages -1)) && !last_odd_page_vld ) ##last odd page not valid
##{
##   tlb->tlb[i].entrylo1 = 0;
##   entry_lo1.reg.field.v = 0;
##}    
##else
##   tlb->tlb[i].entrylo1 = entry_lo1.reg.all;  

.data  
    str_index:	 .asciiz "index: "
	str_entryhi:	 .asciiz "enryhi: "
	str_entrylo0: .asciiz "enrylo0: "
	str_entrylo1: .asciiz "enrylo1: "
	str_pagemask: .asciiz "pagemask: "
	str_newline:  .asciiz "\n"
	str_size:  .asciiz "size:"
	

#define MAP_TLB_BASE    0xC0000000
#define TLB_4K_PAGE_OFFSET 12 
#define ENTRYHI_DEFAULT 0x0
#define TLB_ENTRYLO_DEFAULT_G ( (5<< TLB_ENTRYLO_C_OFFSET) | (1<< TLB_ENTRYLO_D_OFFSET) | (1<< TLB_ENTRYLO_V_OFFSET) | (1<< TLB_ENTRYLO_G_OFFSET))
#define TLB_ENTRYLO_DEFAULT_P ( (5<< TLB_ENTRYLO_C_OFFSET) | (1<< TLB_ENTRYLO_D_OFFSET) | (1<< TLB_ENTRYLO_V_OFFSET) )


.text
	.globl __start    # declaration of main as a global variable

__start:	
	li $t6, 0x20060000
	li $t0, 154333

_set_tlb_global:		
    #EntryHi:
	#---------------------------------
	#| 31        13| 12   8 | 7    0 |
	#|    VPN2     |  0   0 |  ASID  |
	#---------------------------------
	#Entrylo0/1
	#---------------------------------
	#| 31        6| 5  3 | 2 | 1 | 0 |
	#| PFN        |  C   | D | V | G |
	#---------------------------------
	#Mask
	#---------------------------------
	#| 31  29| 28      13| 12     0 |
	#| 0    0|    Mask   | 0      0 |
	#---------------------------------
	#t0 -- MPE shared code/data size need to map 
	#t1 -- Index
	#t2-- entryhi
	#t3 -- entrylo
	#t4 -- asid
	#t5 -- pagemask
	#t6 -- physical address, virtual address is harded coded here, ie, 0xc000 0000
	#V0 -- tmp register
	
	#prepare $t1 for Index
	li $t1, 0
	
	#prepare $t2 for entryhi	
	li $t2, 0xC0000000    
	
	#prepare $t3 for entrylo
	add $t3, $t6, 0     #PHYsical base
	srl $t3, $t3, 12    #TLB_4K_PAGE_OFFSET
	sll $t3, $t3, 6     #TLB_ENTRYLO_PFN_OFFSET
	addi $t3, $t3, 0x2f #TLB_ENTRYLO_DEFAULT_G
	
	#$t4 for asid
	li $t4, 0
	
	#$t5 for pagemask
	li $t5, 0
	
tlb_g_loop:		
	ble $t0, 0, _set_tlb_global_done
	nop
	
	#print size
		li	$v0, 4
		la	$a0, str_size
		syscall	
		li	$v0, 1
		addi $a0, $t0, 0
		syscall
		li	$v0, 4
		la	$a0, str_newline
		syscall
	
	#write even index
		li	$v0, 4
		la	$a0, str_index
		syscall	
		li	$v0, 1
		addi $a0, $t1, 0
		syscall
		li	$v0, 4
		la	$a0, str_newline
		syscall
	
	#write even entryhi
		li	$v0, 4
		la	$a0, str_entryhi
		syscall	
		li	$v0, 1
		addi $a0, $t2, 0
		syscall
		li	$v0, 4
		la	$a0, str_newline
		syscall
		
	#write even entrylo0	
		li	$v0, 4
		la	$a0, str_entrylo0
		syscall	
		li	$v0, 1
		addi $a0, $t3, 0
		syscall
		li	$v0, 4
		la	$a0, str_newline
		syscall
	#write even pagemask
		li	$v0, 4
		la	$a0, str_pagemask
		syscall	
		li	$v0, 1
		addi $a0, $t5, 0
		syscall
		li	$v0, 4
		la	$a0, str_newline
		syscall
	#wlbwt
	
	#update odd page
	addi $t3, $t3, 0x40
	#write entrylo1	
		li	$v0, 4
		la	$a0, str_entrylo1
		syscall	
		li	$v0, 1
		addi $a0, $t3, 0
		syscall
		li	$v0, 4
		la	$a0, str_newline
		syscall
	#wlbwt
	
	#prepare next tlb index--
	#update size $t0 reduce 2 * 4K since one tlb support 2 pages
	li $v0, 0x2000
	sub $t0, $t0, $v0
	
	#update index $t1
	li $v0, 1
	add $t1, $t1, $v0
	
	#update entryhi $t2
	addi $t2, $t2, 0x2000 #(2<<TLB_ENTRYHI_VPN2_OFFSET)
	
	#update entrylo $t3
	addi $t3, $t3, 0x40
			
	li	$v0, 4
	la	$a0, str_newline
	syscall
	
	j tlb_g_loop
	nop
	

_set_tlb_global_done:
	li	$v0, 10	
	syscall