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mywiki:hw:mips:barrier_fence [2014/07/28 14:18] – shaoguohmywiki:hw:mips:barrier_fence [2022/04/02 17:29] (current) – external edit 127.0.0.1
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-**MIPS Pipeline Hazards and Memory Barrier/Fences**+**MIPS Pipeline Hazards, Memory Alignment and Barrier/Fences**
 ====== Pipeline Hazards/Branch Delay ====== ====== Pipeline Hazards/Branch Delay ======
 +{{:mywiki:hw:mips:800px-mips_architecture_pipelined_.svg.png?600|}}
 MIPS has explicit pipeline hazards; **the instruction immediately following a branch or jump instruction will always be executed** (this instruction is sometimes referred to as the "b**ranch delay slot**"). If your code was really assembled exactly as you wrote it: MIPS has explicit pipeline hazards; **the instruction immediately following a branch or jump instruction will always be executed** (this instruction is sometimes referred to as the "b**ranch delay slot**"). If your code was really assembled exactly as you wrote it:
 <file> <file>
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    nop                   #must add nop here    nop                   #must add nop here
 </file> </file>
 +
 +====== Memory Alignment ======
 +Most RISC processors will generate **an alignment fault** when a load or store instruction accesses a **misaligned address**. This allows **the operating system to emulate the misaligned access** using other instructions. For example, the alignment fault handler might use byte loads or stores (which are always aligned) to emulate a larger load or store instruction.
 +
 +Some architectures like MIPS have special unaligned load and store instructions. One unaligned load instruction gets the bytes from the memory word with the lowest byte address and another gets the bytes from the memory word with the highest byte address. Similarly, store-high and store-low instructions store the appropriate bytes in the higher and lower memory words respectively.
 +
 ====== Memory Barrier/Fences ====== ====== Memory Barrier/Fences ======
  
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 CPU cores contain multiple execution units.  For example, a modern Intel CPU contains 6 execution units which can do a combination of arithmetic, conditional logic, and memory manipulation.  Each execution unit can do some combination of these tasks.  These execution units operate in parallel allowing instructions to be executed in parallel.  This introduces another level of non-determinism to program order if it was observed from another CPU. CPU cores contain multiple execution units.  For example, a modern Intel CPU contains 6 execution units which can do a combination of arithmetic, conditional logic, and memory manipulation.  Each execution unit can do some combination of these tasks.  These execution units operate in parallel allowing instructions to be executed in parallel.  This introduces another level of non-determinism to program order if it was observed from another CPU.
  
-{{ ::cpu.png |}}+{{:mywiki:hw:mips:cpu.png|}} 
  
 Loads and stores to the caches and main memory are buffered and re-ordered using the load, store, and write-combining buffers.  These buffers are associative queues that allow fast lookup.  This lookup is necessary when a later load needs to read the value of a previous store that has not yet reached the cache.  Figure 1 above depicts a simplified view of a modern multi-core CPU.  It shows how the execution units can use the local registers and buffers to manage memory while it is being transferred back and forth from the cache sub-system. Loads and stores to the caches and main memory are buffered and re-ordered using the load, store, and write-combining buffers.  These buffers are associative queues that allow fast lookup.  This lookup is necessary when a later load needs to read the value of a previous store that has not yet reached the cache.  Figure 1 above depicts a simplified view of a modern multi-core CPU.  It shows how the execution units can use the local registers and buffers to manage memory while it is being transferred back and forth from the cache sub-system.
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 ====== MIPS Linux barrier ====== ====== MIPS Linux barrier ======
 +Refer to: Linux/arch/mips/include/asm/barrier.h
 <file> <file>
 define __sync()                                \ define __sync()                                \
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                 ".set   push\n\t"               \                 ".set   push\n\t"               \
                 ".set   noreorder\n\t"          \                 ".set   noreorder\n\t"          \
-                 ".set   mips2\n\t"              \ +                ".set   mips2\n\t"              \ 
-                 "sync\n\t"                      \+                "sync\n\t"                      \ 
 +                ".set   pop"                    \ 
 +                : /* no output */               \ 
 +                : /* no input */                \ 
 +                : "memory") 
 + 
 + 
 +#define __fast_iob()                            \ 
 +         __asm__ __volatile__(                   \ 
 +                 ".set   push\n\t"               \ 
 +                 ".set   noreorder\n\t"          \ 
 +                 "lw     $0,%0\n\t"              \ 
 +                 "nop\n\t"                       \
                  ".set   pop"                    \                  ".set   pop"                    \
                  : /* no output */               \                  : /* no output */               \
-                 : /* no input */                \+                 : "m" (*(int *)CKSEG1)          \
                  : "memory")                  : "memory")
-</file>+                  
 +# define fast_wmb()     __sync() 
 +# define fast_rmb()     __sync() 
 +# define fast_mb()      __sync() 
 +                  
 +#define wmb()           fast_wmb() 
 +#define rmb()           fast_rmb() 
 +#define mb()            wbflush() 
 +#define iob()           wbflush()
  
 +#define set_mb(var, value) ...
 +#define smp_llsc_mb() ...
 +
 +</file>
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