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mywiki:hw:mips:barrier_fence [2014/07/28 21:02] – shaoguohmywiki:hw:mips:barrier_fence [2022/04/02 17:29] (current) – external edit 127.0.0.1
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 **MIPS Pipeline Hazards, Memory Alignment and Barrier/Fences** **MIPS Pipeline Hazards, Memory Alignment and Barrier/Fences**
 ====== Pipeline Hazards/Branch Delay ====== ====== Pipeline Hazards/Branch Delay ======
-{{:mywiki:hw:mips:800px-mips_architecture_pipelined_.svg.png?400|}}+{{:mywiki:hw:mips:800px-mips_architecture_pipelined_.svg.png?600|}}
 MIPS has explicit pipeline hazards; **the instruction immediately following a branch or jump instruction will always be executed** (this instruction is sometimes referred to as the "b**ranch delay slot**"). If your code was really assembled exactly as you wrote it: MIPS has explicit pipeline hazards; **the instruction immediately following a branch or jump instruction will always be executed** (this instruction is sometimes referred to as the "b**ranch delay slot**"). If your code was really assembled exactly as you wrote it:
 <file> <file>
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