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--- mywiki:hw:mips:start [2014/07/28 13:49] – shaoguoh
+++ mywiki:hw:mips:start [2022/04/02 17:29] (current) – external edit 127.0.0.1
@@ Line 1: / Line 1: @@
 MIPS
-| [[http://logos.cs.uic.edu/366/notes/mips%20quick%20tutorial.htm#RegisterDescription|MIPS quick Tutoria]] | {{:mywiki:hw:mips:pcspim-tutorial.pdf|}} | [[TLB]] | [[Barrier_Fence|Barrier/Fence/Pipeline Hazards]] |
+| [[http://logos.cs.uic.edu/366/notes/mips%20quick%20tutorial.htm#RegisterDescription|MIPS quick Tutoria]] | {{:mywiki:hw:mips:pcspim-tutorial.pdf|}} | [[TLB]] | [[Barrier_Fence|Barrier/Pipeline Hazards/Align]] | [[LinkScript|Link Script Guide]]  | [[cache]] |
-| [[MipsSimulator]] |
+| [[MipsSimulator]] |  {{:mywiki:hw:mips:cs50-asm.pdf|MIPS ASM Programming}} | {{:mywiki:hw:mips:mips-iv.pdf| MIPS IV Instruction Set}} | {{:mywiki:hw:mips:mips_exception.pdf| MIPS exception}} | {{:mywiki:hw:mips:mips_vol3.pdf| MIPS Vol3}} |
+====== Common Instruction ======
+For details, refer to below documents:
+  * {{:mywiki:hw:mips:mips-iv.pdf| MIPS IV Instruction Set}}
+  * [[http://en.wikipedia.org/wiki/MIPS_instruction_set#MIPS_assembly_language]]
+===== Normal CPU Load/Store Instructions =====
+| LB | Load Byte |
+| LBU | Load Byte Unsigned |
+| SB Store | Byte |
+| LH | Load Halfword |
+| LHU | Load Halfword Unsigned |
+| SH | Store Halfword |
+| LW | Load Word |
+| LWU | Load Word Unsigned |
+| SW | Store Word |
+| LD | Load Doubleword |
+| SD | Store Doubleword |
+===== Unaligned CPU Load/Store Instructions =====
+  * MIPS permits LWL and LWR instructions targeting the same destination register to be executed sequentially.
+  * Store instructions select the correct bytes from a source register and update only those bytes in an aligned memory word (or doubleword)
+| LWL | Load Word Left |
+| LWR | Load Word Right |
+| SWL | Store Word Left |
+| SWR | Store Word Right |
+| LDL | Load Doubleword Left |
+| LDR | Load Doubleword Right |
+| SDL | Store Doubleword Left |
+| SDR | Store Doubleword Right |
+===== Atomic Update CPU Load/Store Instructions =====
+| LL | Load Linked Word |
+| SC | Store Conditional Word |
+| LLD | Load Linked Doubleword |
+| SCD | Store Conditional Doubleword |
+===== Shift Instructions =====
+<file>
+ROTR Rotate Word Right
+SLL Shift Word Left Logical
+SLLV hift Word Left Logical Variable
+SRL Shift Word Right Logical
+SRA Shift Word Right Arithmetic
+ROTRV Rotate Word Right Variable
+SLLV Shift Word Left Logical Variable
+SRLV Shift Word Right Logical Variable
+SRAV Shift Word Right Arithmetic Variable
+DSLL Doubleword Shift Left Logical
+DSRL Doubleword Shift Right Logical
+DSRA Doubleword Shift Right Arithmetic
+DSLL32 Doubleword Shift Left Logical + 32
+DSRL32 Doubleword Shift Right Logical + 32
+DSRA32 Doubleword Shift Right Arithmetic + 32
+DSLLV Doubleword Shift Left Logical Variable
+DSRLV Doubleword Shift Right Logical Variable
+DSRAV Doubleword Shift Right Arithmetic Variable
+</file>
+===== PC-Relative Conditional Branch Instructions Comparing 2 Register =====
+<file>
+EQ Branch on Equal MIPS
+BNE Branch on Not Equal
+BLEZ Branch on Less Than or Equal to Zero
+BGTZ Branch on Greater Than Zero
+BEQL Branch on Equal Likely
+BNEL Branch on Not Equal Likely
+BLEZL Branch on Less Than or Equal to Zero Likely
+BGTZL Branch on Greater Than Zero Likely
+</file>
+===== PC-Relative Conditional Branch Instructions Comparing Against Zero =====
+<file>
+BLTZ Branch on Less Than Zero
+BGEZ Branch on Greater Than or Equal to Zero
+BLTZAL Branch on Less Than Zero and Link
+BGEZAL Branch on Greater Than or Equal to Zero and Link
+BLTZL Branch on Less Than Zero Likely
+BGEZL Branch on Greater Than or Equal to Zero Likely
+BLTZALL Branch on Less Than Zero and Link Likely
+BGEZALL Branch on Greater Than or Equal to Zero and Link Likely
+</file>
+=====  Serialization Instructions =====
+| sync | Loads and stores executed before the SYNC are completed before loads
+and stores after the SYNC can start. |
+=====  Prefetch =====
+here are two prefetch advisory instructions; one with register+offset addressing
+and the other with register+register addressing. These instructions advise that
+memory is likely to be used in a particular way in the near future and should be
+CPU Instruction Set MIPS IV Instruction Set. Rev 3.2 -11
+prefetched into the cache. The PREFX instruction using register+register
+addressing mode is coded in the FPU opcode space along with the other
+operations using register+register addressing.
+Prefetch Using Register + Offset Address Mode
+| PREF | Prefetch Indexed |
+Prefetch Using Register + Register Address Mode
+| PREFX | Prefetch Indexed  |
 ====== MIPS C and Assembly ======
 ===== If/then/else =====