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--- mywiki:hw:mips:start [2014/07/28 14:38] – [Shift Instructions] shaoguoh
+++ mywiki:hw:mips:start [2022/04/02 17:29] (current) – external edit 127.0.0.1
@@ Line 1: / Line 1: @@
 MIPS
-| [[http://logos.cs.uic.edu/366/notes/mips%20quick%20tutorial.htm#RegisterDescription|MIPS quick Tutoria]] | {{:mywiki:hw:mips:pcspim-tutorial.pdf|}} | [[TLB]] | [[Barrier_Fence|Barrier/Fence/Pipeline Hazards]] |
+| [[http://logos.cs.uic.edu/366/notes/mips%20quick%20tutorial.htm#RegisterDescription|MIPS quick Tutoria]] | {{:mywiki:hw:mips:pcspim-tutorial.pdf|}} | [[TLB]] | [[Barrier_Fence|Barrier/Pipeline Hazards/Align]] | [[LinkScript|Link Script Guide]]  | [[cache]] |
-| [[MipsSimulator]] |
+| [[MipsSimulator]] |  {{:mywiki:hw:mips:cs50-asm.pdf|MIPS ASM Programming}} | {{:mywiki:hw:mips:mips-iv.pdf| MIPS IV Instruction Set}} | {{:mywiki:hw:mips:mips_exception.pdf| MIPS exception}} | {{:mywiki:hw:mips:mips_vol3.pdf| MIPS Vol3}} |
 ====== Common Instruction ======
+For details, refer to below documents:
+  * {{:mywiki:hw:mips:mips-iv.pdf| MIPS IV Instruction Set}}
+  * [[http://en.wikipedia.org/wiki/MIPS_instruction_set#MIPS_assembly_language]]
 ===== Normal CPU Load/Store Instructions =====
@@ Line 42: / Line 46: @@
 ===== Shift Instructions =====
 <file>
+ROTR Rotate Word Right
 SLL Shift Word Left Logical
+SLLV hift Word Left Logical Variable
 SRL Shift Word Right Logical
 SRA Shift Word Right Arithmetic
+ROTRV Rotate Word Right Variable
 SLLV Shift Word Left Logical Variable
 SRLV Shift Word Right Logical Variable
@@ Line 82: / Line 89: @@
 BGEZALL Branch on Greater Than or Equal to Zero and Link Likely
 </file>
+=====  Serialization Instructions =====
+| sync | Loads and stores executed before the SYNC are completed before loads
+and stores after the SYNC can start. |
+=====  Prefetch =====
+here are two prefetch advisory instructions; one with register+offset addressing
+and the other with register+register addressing. These instructions advise that
+memory is likely to be used in a particular way in the near future and should be
+CPU Instruction Set MIPS IV Instruction Set. Rev 3.2 -11
+prefetched into the cache. The PREFX instruction using register+register
+addressing mode is coded in the FPU opcode space along with the other
+operations using register+register addressing.
+Prefetch Using Register + Offset Address Mode
+| PREF | Prefetch Indexed |
+Prefetch Using Register + Register Address Mode
+| PREFX | Prefetch Indexed  |
 ====== MIPS C and Assembly ======
 ===== If/then/else =====