MIPS
| MIPS quick Tutoria | pcspim-tutorial.pdf | TLB | Barrier/Pipeline Hazards/Align | Link Script Guide | cache |
| MipsSimulator | MIPS ASM Programming | MIPS IV Instruction Set | MIPS exception | MIPS Vol3 |
For details, refer to below documents:
| LB | Load Byte |
| LBU | Load Byte Unsigned |
| SB Store | Byte |
| LH | Load Halfword |
| LHU | Load Halfword Unsigned |
| SH | Store Halfword |
| LW | Load Word |
| LWU | Load Word Unsigned |
| SW | Store Word |
| LD | Load Doubleword |
| SD | Store Doubleword |
| LWL | Load Word Left |
| LWR | Load Word Right |
| SWL | Store Word Left |
| SWR | Store Word Right |
| LDL | Load Doubleword Left |
| LDR | Load Doubleword Right |
| SDL | Store Doubleword Left |
| SDR | Store Doubleword Right |
| LL | Load Linked Word |
| SC | Store Conditional Word |
| LLD | Load Linked Doubleword |
| SCD | Store Conditional Doubleword |
ROTR Rotate Word Right SLL Shift Word Left Logical SLLV hift Word Left Logical Variable SRL Shift Word Right Logical SRA Shift Word Right Arithmetic ROTRV Rotate Word Right Variable SLLV Shift Word Left Logical Variable SRLV Shift Word Right Logical Variable SRAV Shift Word Right Arithmetic Variable DSLL Doubleword Shift Left Logical DSRL Doubleword Shift Right Logical DSRA Doubleword Shift Right Arithmetic DSLL32 Doubleword Shift Left Logical + 32 DSRL32 Doubleword Shift Right Logical + 32 DSRA32 Doubleword Shift Right Arithmetic + 32 DSLLV Doubleword Shift Left Logical Variable DSRLV Doubleword Shift Right Logical Variable DSRAV Doubleword Shift Right Arithmetic Variable
EQ Branch on Equal MIPS BNE Branch on Not Equal BLEZ Branch on Less Than or Equal to Zero BGTZ Branch on Greater Than Zero BEQL Branch on Equal Likely BNEL Branch on Not Equal Likely BLEZL Branch on Less Than or Equal to Zero Likely BGTZL Branch on Greater Than Zero Likely
BLTZ Branch on Less Than Zero BGEZ Branch on Greater Than or Equal to Zero BLTZAL Branch on Less Than Zero and Link BGEZAL Branch on Greater Than or Equal to Zero and Link BLTZL Branch on Less Than Zero Likely BGEZL Branch on Greater Than or Equal to Zero Likely BLTZALL Branch on Less Than Zero and Link Likely BGEZALL Branch on Greater Than or Equal to Zero and Link Likely
| sync |
and stores after the SYNC can start. |
here are two prefetch advisory instructions; one with register+offset addressing and the other with register+register addressing. These instructions advise that memory is likely to be used in a particular way in the near future and should be CPU Instruction Set MIPS IV Instruction Set. Rev 3.2 -11 prefetched into the cache. The PREFX instruction using register+register addressing mode is coded in the FPU opcode space along with the other operations using register+register addressing.
Prefetch Using Register + Offset Address Mode
| PREF | Prefetch Indexed |
Prefetch Using Register + Register Address Mode
| PREFX | Prefetch Indexed |
| C Conditional Operator | MIPS Assembly Instruction |
| a==b | beq $t0,$t1,then |
| a != b | bne $t0, $t1, then |
| a < b | blt $t0, $t1, then |
| a > b | bgt $t0, $t1, then |
| a⇐b | ble $t0,$t1,then |
| a>=b | bge $t0,$t1,then |
| a == 0 | beqz $t0, then |
| C Loop | Assembly loop |
int i;
for( i=0;i<10;i++ ) {
loop body
}
int i=0;
while (i<10){
loop body
i++;
}
|
|
strlen: li $t0, 0 #initialize the count to zero loop: lbu $t1, 0($a0) # load the next character into t1 beqz $t1, exit # check for the null character addi $a0, $a0, 1 # increment the string pointer addi $t0, $t0, 1 # increment the count j loop # return to the top of the loop exit:
max:
lw $t0, 0($a0) # load the first array value into t0
li $t1, 1 # initialize the counter to one
loop:
beq $t1, $a1, exit #exit if we reach the end of the array
addi $a0, $a0, 4 #increment the pointer by one word
addi $t1, $t1, 1 #increment the loop counter
lw $t2, 0($a0) #store the next array value into t2
ble $t2, $t0, end_if
move $t0, $t2 #found a new maximum, store it in t0
end_if:
j loop #repeat the loop
exit:
| jal | jump and link | saves the return address (the address of the next instruction, ie $PC + 4) in the dedicated register $ra, before jumping to the function |
| jr | jump and return | To transfer control back to the caller, the function just has to jump to the address that was stored in $ra |
The caller is responsible for saving/restoring any of the following caller-saved registers:
The callee is responsible for saving/restoring any of the following callee-saved registers:
$ra is special; it is “used” by jal. It is saved by a callee who is also a caller.
| $sp | stack pointer points to the top of the stack. |
| $fp | frame pointer ($fp) points to the start of the stack frame and does not move for the duration of the subroutine call. This points to the base of the stack frame, and the parameters that are passed in to the subroutine remain at a constant spot relative to the frame pointer |
sub $sp, $sp, 8 sw $t1, 4($sp) sw $t2, 0($sp) An equivalent sequence is: sw $t1, -4($sp) sw $t2, -8($sp) sub $sp, $sp, 8
lw $s0, 4($sp)
addi $sp, $sp, 8
_start:
#save registers
sw $t1, -4($sp)
sw $t2, -8($sp)
sw $v1, -12($sp)
sw $v2, -16($sp)
sub $sp, $sp, 16
#set function parameters
li $a1, 4 #set function parameters
#call function/subroutine
jal func1
#restore saved registers
lw $t1, -4($sp)
lw $t2, -8($sp)
lw $v1, -12($sp)
lw $v2, -16($sp)
addi $sp, $sp, 16
#use return value $v1/v2
....
func1: ....
#prepare returned value in $v1/$v2
sw $v1, 10
sw $v1, 100
#return to the caller
jr $ra